2m x 8 static ram cy7c1069av33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05255 rev. *f revised august 3, 2006 features ?high speed ?t aa = 10, 12 ns ? low active power ? 990 mw (max.) ? operating voltages of 3.3 0.3v ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce 1 and ce 2 features ? available in pb-free and non pb-free 54-pin tsop ii , non pb-free 60-ball fine-pitch ball grid array (fbga) package functional description the cy7c1069av33 is a high-performance cmos static ram organized as 2,097,152 words by 8 bits. writing to the device is accomplished by enabling the chip (by taking ce 1 low and ce 2 high) and write enable (we ) inputs low. reading from the device is accomplished by enabling the chip (ce 1 low and ce 2 high) as well as forcing the output enable (oe ) low while forcing the write enable (we ) high. see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c1069av33 is available in a 54-pin tsop ii package with center power and ground (r evolutionary) pinout, and a 60-ball fine-pitch ball grid array (fbga) package. logic block diagram top view tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 43 42 16 15 29 30 a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 7 a 2 ce 1 i/o 0 i/o 1 a 3 a 4 18 17 20 19 27 28 25 26 22 21 23 24 i/o 2 i/o 3 a 16 a 15 v cc i/o 6 nc i/o 5 i/o 4 a 14 a 13 a 12 a 11 a 9 a 10 ce 2 44 46 45 47 50 49 48 51 53 52 54 v ss v cc a 19 a 18 v cc v cc v ss dnu v ss nc v cc v ss nc nc nc nc nc nc nc nc a 20 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 2048k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 14 a 13 a 17 a 19 a 15 a 16 a 9 a 18 ce 1 ce 2 a 10 a 11 a 12 a 20 pin configurations [1, 2] [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 2 of 9 notes: 1. nc pins are not connected on the die. 2. dnu pins have to be left floating or tied to vss to ensure proper application. selection guide ?10 ?12 unit maximum access time 10 12 ns maximum operating current 275 260 ma maximum cmos standby current 50 50 ma pin configurations [1, 2] (continued) 60-ball fbga we v cc a 11 a 10 a 6 a 0 a 3 ce 1 i/o 0 a 4 a 5 i/o 1 i/o 2 i/o 3 nc v ss a 9 a 8 oe v ss a 7 nc ce2 a 17 a 2 a 1 v cc i/o 4 i/o 5 i/o 6 i/o 7 nc a 15 a 14 a 13 a 12 dnu 3 2 6 5 4 1 d e b a c f g h (top view) a 16 a 19 a 20 nc nc nc nc a 18 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 0.3v industrial ?40 c to +85 c dc electrical characteristics over the operating range parameter description test conditions ?10 ?12 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc 275 260 ma i sb1 automatic ce power-down current ?ttl inputs ce 2 < v il , max. v cc , ce 1 > v ih v in > v ih or v in < v il , f = f max 70 70 ma i sb2 automatic ce power-down current ?cmos inputs ce 2 < 0.3v, max. v cc , ce 1 > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 50 50 ma capacitance [4] parameter description test conditions tsop ii fbga unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 6 8 pf c out i/o capacitance 8 10 pf ac test loads and waveforms [5] notes: 3. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 4. tested initially and after any design or proc ess changes that may affect these parameters. 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). as soon as 1ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 90% 10% 3.3v gnd 90% 10% all input pulses 3.3v output 5 pf* *including jig and scope (a) (b) r1 317 ? r2 351 ? rise time > 1v/ns fall time: > 1v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5v 30 pf* *capacitive load consists of all components of the test environment [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 4 of 9 ac switching characteristics over the operating range [7] parameter description ?10 ?12 unit min. max. min. max. read cycle t power v cc (typical) to the first access [8] 11 ms t rc read cycle time 10 12 ns t aa address to data valid 10 12 ns t oha data hold from address change 3 3 ns t ace ce 1 low/ce 2 high to data valid 10 12 ns t doe oe low to data valid 5 6 ns t lzoe oe low to low-z [9] 11 ns t hzoe oe high to high-z [ 9 ] 56 ns t lzce ce 1 low/ce 2 high to low-z [9] 33 ns t hzce ce 1 high/ce 2 low to high-z [ 9] 56 ns t pu ce 1 low/ce 2 high to power-up [10] 00 ns t pd ce 1 high/ce 2 low to power-down [10] 10 12 ns write cycle [10, 11] t wc write cycle time 10 12 ns t sce ce 1 low/ce 2 high to write end 7 8 ns t aw address set-up to write end 7 8 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 7 8 ns t sd data set-up to write end 5.5 6 ns t hd data hold from write end 0 0 ns t lzwe we high to low-z [9] 33 ns t hzwe we low to high-z [ 9 ] 56 ns data retention waveform notes: 6. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). as soon as 1ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and transmission line loads. test conditions for the read cycle use output loading shown in part a) of the ac test loads, unle ss specified otherwise. 8. this part has a voltage regulator which steps down the voltage from 3v to 2v internally. t power time has to be provided initially before a read/write operation is started. 9. t hzoe , t hzsce , t hzwe and t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 200 mv from steady-state voltage. 10. these parameters are guaranteed by design and are not tested. 11. the internal write time of the memory is defined by the overlap of ce 1 low/ce 2 high , and we low. ce 1 and we must be low along with ce 2 high to initiate a write, and the transition of any of these signals can terminat e the write. the input data set-up and hold timing should be re ferenced to the leading edge of the signal that terminates the write. 12. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 5 of 9 switching waveforms read cycle no. 1 [13, 14] read cycle no. 2 (oe controlled) [14, 15] notes: 13. device is continuously selected. ce 1 = v il , ce 2 = v ih . 14. we is high for read cycle. 15. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t asce t doe t lzoe t lzsce t pu high impedance t hzoe t pd high oe ce 1 impedance address data out v cc supply t hzsce current i cc i sb ce 2 [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 6 of 9 write cycle no. 1 (ce 1 controlled) [16, 17, 18] write cycle no. 2 (we controlled, oe low) [16, 17, 18] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we t t hd t sd t sce t ha t aw t pwe t wc data i/o address ce we t sa t lzwe t hzwe truth table ce 1 ce 2 oe we i/o 0 ?i/o 7 mode power h x x x high-z power-down standby (i sb ) x l x x high-z power-down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high-z selected, outputs disabled active (i cc ) notes: 16. data i/o is high-impedance if oe = v ih . 17. if ce 1 goes high/ce 2 low simultaneously with we going high, the output remains in a high?impedance state. 18. ce above is defined as a combination of ce 1 and ce 2 . it is active low. [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 7 of 9 package diagrams ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1069av33-10zc 51-85160 54-pin tsop ii commercial cy7c1069av33-10zxc 54-pin tsop ii (pb-free) cy7c1069av33-10bac 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) fbga cy7c1069av33-10zi 51-85160 54-pin tsop ii industrial cy7c1069av33-10zxi 54-pin tsop ii (pb-free) cy7c1069av33-10bai 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) fbga 12 cy7c1069av33-12zc 51-85160 54-pin tsop ii commercial cy7c1069av33-12zxc 54-pin tsop ii (pb-free) cy7c1069av33-12bac 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) fbga cy7c1069av33-12zi 51-85160 54-pin tsop ii industrial CY7C1069AV33-12ZXI 54-pin tsop ii (pb-free) cy7c1069av33-12bai 51-85162 60-ball (8 mm x 20 mm x 1.2 mm) fbga 51-85160-** 54-pin tsop ii (51-85160) [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) all product and company names mentio ned in this document may be the tr ademarks of their respective holders dimensions in mm part # ba60a standard pkg. bk60a lead free pkg. pkg weight: 0.30 gms a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25mcab ?0.05mc b a 0.15(4x) 0.210.05 1.20 max c seating plane 0.530.05 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f 65 46 5 23 1 8.000.10 20.000.10 a 20.000.10 8.000.10 b 1.875 2.625 g h d g h e f b c a 18.00 6.00 dummy ball (0.3) x12 0.36 0.75 1.00 0.75 1.00 60-ball fbga (8 mm x 20 mm x 1.2 mm) (51-85162) 51-85162-*d [+] feedback [+] feedback
cy7c1069av33 document #: 38-05255 rev. *f page 9 of 9 document history page document title: cy7c1069av33 2m x 8 static ram document number: 38-05255 rev. ecn no. issue date orig. of change description of change ** 113724 03/27/02 nsl new data sheet *a 117060 07/31/02 dfp removed 15-ns bin *b 117990 08/30/02 dfp added 8-ns bin changing i cc for 8, 10, 12 bins t power changed from 1 s to 1 ms load cap comment changed (for tx line load) t sd changed to 5.5 ns for the 10-ns bin changed some 8-ns bin #'s (t hz , t doe , t dbe ) removed hz < lz comments *c 120385 11/13/02 dfp final data sheet added note 4 to ?ac test loads and waveforms? and note 7 to t pu and t pd updated input/output caps (for 48bga only) to 8 pf/10 pf and for the 54-pin tsop to 6/8 pf *d 124441 2/25/03 meg changed isb1 from 100 ma to 70 ma shaded the 48fbga product offering information *e 403984 see ecn nxr changed the logic block diagram on page # 1 added notes under pin configuration changed the package diagram of 51-85162 from rev *a to rev *d changed 48-ball fbga to 60-ball fbga in pin configuration updated the ordering information *f 492137 see ecn nxr removed 8 ns speed bin from product offering changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated the ordering information [+] feedback [+] feedback
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